The present invention relates to a semiconductor integrated circuit device, such as a semiconductor memory device, e.g., a static random access memory (SRAM) having memory cells.
In a conventional semiconductor memory device, memory cells are arranged to form a matrix, and one of the memory cells is selected through selection of one of the word lines and one of the pairs of bit lines, and the data is read from or written in the selected memory cell. This is described in more detail with reference to FIG. 1 and FIG. 2.
FIG. 1 shows part of the circuit of a conventional semiconductor memory device, which is an SRAM. It has a plurality of word lines WL. (only two being illustrated), and a plurality of pairs of bit lines BLa, BLb (only two pairs being illustrated). The word lines WL and bit lines BLa and BLb are selected in accordance with an address. Memory cells MC (only four being illustrated), are disposed at intersections between the word lines and the bit lines, arranged to form a matrix, and connected to the word lines and the bit lines. As illustrated In FIG. 1A, each of the memory cells MC comprises a flip-flop circuit including a pair of n-channel metal-oxide-silicon (n-channel MOS or NMOS) transistors 11 and 12 which are cross-coupled with each other, i.e., each having its gate electrode connected to the drain electrode of the other transistor. The drains of the transistors 11 and 12 are connected via load resisters 13 and 14 to a power supply node Vcc. The sources of the transistors 11 and 12 are connected to a ground potential node Vss. The transistors 11 and 12 are also connected to a pair of complementary bit lines BLa and BLb via switching means in the form of NMOS transistors 15 and 16.
Referring to FIG. 1, one ends of the pair of bit lines BLa and BLb are connected to the power supply node Vcc via NMOS transistors 21a and 21b acting as load resistors. The other ends of the bit lines are connected to a pair of complementary data lines DLa and DLb via transfer gates in the form of NMOS transistors 22a and 22b, which are turned on and off by column lines CL selected by an address.
As illustrated in FIG. 2, the pair of data lines DLa and DLb are connected to non-inverted input node 31a and inverted input node 31b of a sense amplifier 30 for sensing and amplifying the potential difference between the pair of bit lines. The sense amplifier 30 comprises NMOS transistors 32 and 33 forming a differential amplifier having their gates controlled by input to the non-inverted input node 31a and inverted input node 31b. Drains of the NMOS transistors 32 and 33 are connected to the power supply node Vcc via p-channel MOS (PMOS) transistors 34 and 35 acting as loads. Sources of the NMOS transistors 32 and 33 are connected to the ground node Vss via a constant current source 36. Output nodes at the drains of the NMOS transistors 32 and 33 are connected together via a resetting NMOS transistor 37 which is turned on and off by an address change detection signal .0.a. When the resetting NMOS transistor 37 is on the output nodes 38a and 38b are connected together and the sense amplifier 30 is thereby reset. The address change detection signal .0.a is active at the time of address change, to turn on the NMOS transistor 37 thereby resetting the sense amplifier 30.
The output node 38b of the sense amplifier 30 is connected to an input node 41 of an output transfer gate 40. An output node of the output transfer gate 40 is connected an output latch circuit 50 and an output circuit 60. The output transfer gate 40 is controlled by complementary address change detection signals .0.a and .0.b and transfer the sense amplifier output to the output circuit. It comprises a complementary M0S (CMOS) inverter comprising a PMOS transistor 42a and an NMOS transistor 42b for inverting the potential at the input node 41. The output transfer gate 40 further comprises a PMOS transistor 43 and an NMOS transistor 44 which are turned on and off responsive to the address change detection signals .0.a and .0.b.
The output latch circuit 50 which is connected to the output node of the output transfer gate 40 is controlled by the address change detection signals .0.a and .0.b and latches the output data. It comprises a flip-flop (FF) 51 connected to the output node 45, and a PMOS transistor 52 and an NMOS transistor 53 whose gates are controlled by the address change detection signals .0.a and .0.b. The flip-flop 51 comprises a first series circuit of a PMOS transistor 51a and an NMOS transistor 51c, and a second series circuit of a PMOS transistor 51b and an NMOS transistor 51d, wherein the PMOS and NMOS transistors 51a to 51d are cross-coupled.
The output circuit 60 connected to the output node 45 of the output transfer gate 40 comprises inverters 61 and 62 for inverting the potential of the output node 45, and an output buffer 63 driven by the inverters 61 and 62. The output buffer 63 comprises a PMOS transistor 63a and an NMOS transistor 63b connected in series between the power supply node Vcc and the ground potential node Vss, and the junction between them is connected to an output node 64.
Referring again to FIG. 1, the data lines DLa and DLb are also connected, at first ends thereof, to a write control circuit, an example of which is shown in FIG. 3, via inverters 104 and 105.
As illustrated in FIG. 3, the write control circuit comprises a buffer circuit 110 comprising a plurality of cascaded inverters 111 to 113 and inverting the inverted write enable signal WE, and a write enable delay circuit 120 and a two-input NAND gate 130 which are connected to the output of the buffer circuit 110. The write enable delay circuit 120 delays the inverted write enable signal WE for a predetermined time and comprises cascaded inverters 121 to 124, and capacitors 125 and 126. The two-input NAND gate 130 determines the inversion of the logical product of the output of the write enable delay circuit 120 and the output of the buffer circuit 110, and generates an inverted internal write enable signal W.
The input data Din for use in writing data is passed through a buffer circuit 135 comprising two cascaded inverters 136 and 137, and the output of the buffer circuit 135 is connected to the data input delay circuit 140. The data input delay circuit 140 delays the input data Din for a predetermined time, and generates an internal input data D, and comprises cascaded inverters 141 to 144, and capacitors 145 to 148. The output of the data input delay circuit 140 is connected through a transfer gate 150 to a write amplifier 160.
The transfer gate 150 comprises a CMOS inverter 151 comprising a PMOS transistor 151a and an NMOS transistor 151b and inverting the internal input data D, and a PMOS transistor 152 and an NMOS transistor 153 turning on and off the current flowing through the inverter 151, and an inverter 154 for inverting the inverted internal write enable signal W and applying its output to the gate of the NMOS transistor 153 to control the NMOS transistor 153. The PMOS transistor 152 is turned on and off by the inverted internal write enable signal W. The output of the CMOS inverter 151 is connected to the write amplifier 160 which amplifies the output of the inverter 151 and supplies it to the inverter 104.
Reading operation of the semiconductor memory device of FIG. 2 will now be described with reference to FIG. 4, which shows waveforms of signals at various parts of the circuit of FIG. 2.
When a reading cycle starts, and transition takes place in the address ADD, then the transition is detected by an address change detection circuit, not shown, and the address change detection signals .0.a and .0.b are generated. Then, the address change detection signal .0.a goes High, and the address change detection signal .0.b goes Low. The NMOS transistor 37 in the sense amplifier 30 is turned on and the output nodes 38a and 38b are short-circuited to each other. The output potentials approach the operating point of the sense amplifier 30. Moreover , the PMOS transistor 43 in the output transfer gate 40 is turned off and the NMOS transistor 44 is turned on, so that output node 45 of the output transfer gate 40 is brought into a floating state. Furthermore, the PMOS transistor 52 in the output latch circuit 50 is turned on and the NMOS transistor 54 is turned on, so the FF 51 is operative, to hold the output data derived during the preceding reading cycle, as long as the address change detection signal .0.a is High. The data derived during the preceding is therefore kept outputted at the output node 64 of the output buffer 63.
When transition takes place in the address, the selected word line WL goes High and the selected column line CL goes High, so that the memory cell MC connected to the selected word line WL and the selected column line CL is selected. The NMOS transistors 15 and 16 in the memory cell MC are turned on and the stored data is outputted to the pair of bit lines BLa and BLb. Since the NMOS transistors 22a and 22b are on, the stored data read out of the memory cell MC is passed through the data lines DLa and DLb to the sense amplifier 30.
When the address change detection signal .0.a changes from High to Low, the resetting NMOS transistor 37 in the sense amplifier 30 is turned off and the sensing and amplifying operation of the sense amplifier 30 is started. When the address change detection signal .0.a goes Low and the address change detection signal .0.b goes High, the PMOS transistor 43 and the NMOS transistor 44 in the output transfer gate 40 are turned on and the output of the sense amplifier 30 is passed through the CMOS inverter 42 to the inverters 61 and 62, which respectively invert the output of the output transfer gate 40 and causes the output buffer 63 to operate. An output data then appears at the output node 64 of the output buffer 63, and the reading operation is thus completed. The PMOS transistor 52 and the NMOS transistor 53 of the output latch circuit 50 are both off, so that the FF 51 is in the inactive state and does not give any effect on the output data.
Now, writing operation is next described with reference to FIG. 5, in which t.sub.wc denotes a write cycle time, t.sub.as denotes an address set-up time, t.sub.dh denotes a data hold time (write margin), R denotes the time at which the word line WL is activated (e.g., made to rise). The reference numeral 161 shown a waveform that is obtained when there is no erroneous writing, while reference numeral 162 denotes a waveform that is obtained when there is a possibility of an erroneous writing.
Upon expiration of address set up time t.sub.as after transition of address AD, the inverted write enable signal WE goes Low. When the inverted write enable signal WE goes Low, this is delayed by the write enable delay circuit 120. When input data Din is set up, the input data Din is delayed by the data input delay circuit 140.
The inverted write enable signal WE is delayed by the write enable delay circuit 120 for a predetermined time, and the inverted internal write enable signal W outputted from the two-input NAND gate 130 goes Low, and the PMOS transistor 152 and the NMOS transistor 153 in the transfer gate 150 are turned on, and the inverter 151 is made operative. The input data Din is delayed by the data input delay circuit 140, and the delayed internal input data D is inverted by the inverter 151 and amplified by the write amplifier 160, and passed through the inverters 104 and 105, whose outputs, which are complementary, are supplied to the data lines DLa and DLb.
The address AD is decoded by a decoder, not shown, and the selected word line WL rises at point R in FIG. 5, and the selected memory cell MC is made accessible. When the inverted write enable signal WE rises, it is transmitted to the buffer circuit 110 and the two-input NAND gate 130, and the inverted internal write enable signal W outputted from the two-input NAND gate 130 goes High and the PMOS transistor 152 and the NMOS transistor 153 in the transfer gate 150 are turned off, and the inverter 151 is turned off. As a result, the write data on the data lines DLa and DLb is written in the selected memory cell MC through the transfer gates 22a and 22b selected by the column line CL.
The reason why the write enable delay circuit 120 and the data input delay circuit 140 are provided in the memory write control circuit is as follows:
For instance, If the word lines WL goes High at time point R in FIG. 5, after the inverted write enable signal WE goes Low, the memory cell MC is selected by the previous address until the point R, so if there occurs transition of the input data Din before the time point R, the new input data is written in the memory cell MC selected by the previous address. To avoid this, the write enable delay circuit 120 and the data input delay circuit 140 are provided to delay the inverted write enable signal WE and the input data Din so that they are in time with the rise of the word line WL.
The above described reading circuit did not meet with the requirements of increase in the reading speed, and simplification in the design of the reset timing of the sense amplifier. This is explained next.
In the circuit of FIG. 2, the output node 64 varies only at the termination of the address change detection signal .0.a, so that speed of operation is limited depending on the timing of the address change detection signal .0.a. Moreover, the sense amplifier 30 approaches its operating point whenever it is reset, so that it is possible that erroneous output may be generated depending on the output of the preceding cycle.
The write control circuit described above has the following shortcomings:
As shown in FIG. 3, since the write enable delay circuit 120 and the data input delay circuit 140 are provided in the memory write control circuit to delay the inverted write enable signal WE and the input data Din for respective predetermined times so that they are in time with the rise of the word line, it is difficult to ensure sufficient data hold time t.sub.dh (write margin). As a result, erroneous writing may be caused if the inverted internal write enable signal W rises too late or the transition of the internal input data D is too early.
That is, if the inverted internal write enable signal W goes High before time point R2 in FIG. 5, the internal input data the the time of the rise is written in the selected memory cell MC, so that erroneous writing does not occur as indicated in the waveform 161. If however the inverted internal write enable signal W rises after time point R1, due for instance to the variation in the circuit constants erroneous writing may occur as indicated in waveform 162.